The present invention relates generally to a system for generating an oscillator signal and, more particularly, to a phase-locked loop (PLL) for generating an oscillator signal.
A phase-locked loop (PLL) is a control system that generates an oscillator signal having a constant phase relationship with an input reference signal. PLLs are widely used in various applications such as radios, telecommunications, computers, and other electronic applications. A PLL includes a voltage-controlled oscillator (VCO) for generating the oscillator signal based on a control voltage, and a phase detector for comparing the phase of the oscillator signal with that of the input reference signal and for generating an error signal based on the detected phase difference. The PLL also includes a loop filter for filtering the error signal and generating the control voltage used by the VCO.
For stable operation, the bandwidth of the PLL is required to be dependent only on the frequency of the input reference signal. However, the bandwidth may vary with various other parameters, such as process, voltage and temperature (PVT) variations, loop division factor ‘N’, PLL design parameters and the like. These parameters introduce undesired variance into the PLL bandwidth and degrade the loop stability of the PLL. Further, the input capacitance of the loop filter is known to consume a substantial portion of the overall circuit area.
It would be advantageous to have a PLL whose bandwidth is independent of PVT variations, loop division factor, and PLL design parameters, and dependent only on the frequency of the input reference signal. It would be further advantageous to reduce the area consumed by the input capacitor used in the PLL loop filter.